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Dream logic #9
Dream logic #9
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… PS interlock output and logic
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"DREAM_NC_GCC_01.IG.rPRESS < 1.0E-5 AND
DREAM_DP1_GHC_01.IG.xPRESS_OK AND DREAM_DP1_GHC_01.IG.rPRESS < 1.0E-5;" If the at_vac setpoint will likely change during operation, we should make it user-configurable.
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The logic should be: VRC_02 can be closed only when VRC_01 is open. so we only need to do is: set the VRC_02_ILK := VRC_01.i_xOpnLS, and pass it to the VRC_02 function.
//Close DP1_VRC_02 if DP1_VRC_01 is opened
"IF DREAM_DP1_VRC_01.iq_stValve.i_xOpnLS THEN
DREAM_DP1_VRC_02.M_Set_CLS_SW(TRUE);
END_IF
DREAM_DP1_VRC_02(i_xExtILK_OK := bDP1_VRC_02_ILK, i_xOverrideMode := bSystemOverrideMode); //Normally open valve"
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Using pumpRUNNING estate instead of atSpeed. Since eState is evaluated more strictly: iq_stPtm.i_xAtSpd AND iq_stPtm.q_RunDO THEN iq_stPtm.eState := pumpRUNNING;
"DREAM_MC_GHC.IG_CH1.rPRESS < 1.0E-8 AND
DREAM_CAT1_PTM_01.iq_stPtm.i_xAtSpd AND
DREAM_CAT2_PTM_01.iq_stPtm.i_xAtSpd;"
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Add interlock to the turbopumps estate: pumps are not running.
DREAM_ROUGH1_VFV_02(i_xExtIlkOK := DREAM_ROUGH1_VRC_01.iq_stValve.i_xClsLS AND DREAM_DP1_VRC_01.iq_stValve.i_xClsLS);
DREAM_ROUGH2_VFV_02(i_xExtIlkOK := DREAM_ROUGH2_VRC_01.iq_stValve.i_xClsLS);
DREAM_ROUGH2_VFV_03(i_xExtIlkOK := DREAM_ROUGH2_VRC_02.iq_stValve.i_xClsLS AND DREAM_CAT1_VRC_01.iq_stValve.i_xClsLS);
@jyin999 Please review the changes and approve. Thanks |
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Motivation and Context
How Has This Been Tested?
Where Has This Been Documented?
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